1. Field of Invention
This invention relates to a high reliability non volatile memory cell structure, which can be electrically written and erased for high density, low voltage applications.
2. Description of Prior Art
The current electrically programmable and erasable non volatile memory cells consists of EEPROMs (Electrically Erasable Programmable ROMs) and Flash Memories.
The EEPROMs (FIG. 1) are as the name implies electrically programmable and erasable. They are programmed and erased through a thin oxide area called tunnel area which normally has an oxide thickness between 50 and 120 Angstroms and is grown on top of a doped silicon region, By applying a high voltage across this tunnel oxide the electrons can be made to move to and from a floating gate over the tunnel oxide. The tunnel process is a very slow process and hence the EEPROMs are slow to write and slow to erase. During erase the devices are made to go into depletion by removing electrons from the floating gate. In order to have an array of devices operate in series it is necessary to have an isolation transistor in series with the storage device. The need for a separate tunnel area with diffusion and need for additional isolation transistor make the EEPROM cells large in size and hence unsuitable for high density applications.
The typical Flash Cell (FIG. 2) is a new development and is an electrically erasable programmable ROM cell which use the EPROM or hot write to achieve fast write operation and the tunnel process to erase. A high drain voltage is applied to the cell to generate a large volume of careers by impact ionization at the drain depletion region when the device operates under saturated conditions. The ionized carriers will consist of both electrons and holes and these will have velocities in random directions. The positively charged holes generated during impact ionization, get collected by the substrate and flow to ground producing a large current component which is wasted. A very small percentage of the electrons generated by impact ionization will have velocity component which is in a direction suitable for collection by the floating gate electrode. These will be accelerated towards the floating gate(7a) by the high voltage on the floating gate which is coupled down from the control gate(9a) through the thin insulating layer(Sa). These electrons are collected by the floating gate and are stored in the floating gate providing a net negative charge in the floating gate electrode. The balance of the electrons generated flow to the drain and are returned to the supply. The charge due to the carriers collected by the floating gate modify the threshold of the device indicating a charged state. The erase is accomplished by allowing the electrons to tunnel through the thin gate oxide, typically 50 to 120 A in thickness, by application of a high voltage to one of the junctions, preferably the source junction (4a), while holding the control gate(9a) at low or zero voltage. The erase can also be accomplished by application of a negative voltage to the control gate and simultaneously applying a positive voltage to the source. The tunneling takes place from the floating gate to the source region edge(13a) which is thermally driven under the gate oxide.
The present day Flash cells suffer from a number of problems to achieve low power and low voltage applications. These include but are not limited to:
1. The flash cells need high power supply to provide high current at relatively high voltage to the drain of the flash device. The high voltage is necessary to ensure existence of high fields at the drain depletion region to achieve hot electron generation and high currents are needed to ensure that sufficient electrons with the correct velocity component are available to be collected by the floating gate.
2. Only a small portion of the generated carriers are usable, the balance is wasted as drain current and as substrate current. This is due to the fact that in a typical flash, during hot carrier generation, the generated electrons have random velocities and only those with a velocity component towards the floating gate are collected, the rest being collected by the drain. The generated holes are all collected by the substrate terminal and are removed as non usable.
3. The large substrate current component can cause reliability problems due to latchup in nearby circuits by charging up the substrate.
4. The need for large drain voltages mandate increased spacing requirements between cells, increasing the area required to achieve a given density of memory.
5. The need to use high drain voltage also reduce the horizontal scalability of the cell by requiring a minimum gate length to withstand the applied voltage.
6. Vertical scaling with reduction in gate oxide thickness for improved performance will also create problems for the cell by allowing tunneling at voltages close to the applied drain voltage and hence cause disturb problems.
7. The use of thinner gate oxide in current flash cells make sustaining the field at the drain more difficult and act against the carrier generation need.
8. The inability to thin down the gate oxide due to the need for high field generation at the drain makes the use of high erase voltage a must, typical erase voltages needed is approximately 10 V across a 100 A oxide.